1. Field of the Invention
The present invention provides a multi-transistor layout capable of saving area, and more particularly, a multi-transistor layout with common drains.
2. Description of the Prior Art
As manufacturing processes of VLSI (very large scale integrated) circuits improves, operating frequencies of microprocessors, wireless communication units, etc. become higher and higher. In order to meet such high-frequency demand, improved efficiency of digital to analog converts, or DACs, is expected. In the prior art, a current-steering DAC is a high-speed DAC, whose signal current is switched to different outputs through switch gates.
Please refer to FIG. 1, which illustrates a schematic diagram of a prior art current-steering DAC 10. The current-steering DAC 10 includes common-source differential pairs S1, S2 to SN and corresponding current sources I1, I2 to IN. Each of the common-source differential pairs S1, S2 to SN includes two PMOS transistors (M1+, M1−, M2+, M2− to MN+ and MN− shown in FIG. 1) for forming a switch of a differential pair. According to control signals VC1+, VC1−, VC2+, VC2− to VCN+ and VCN−, the common-source differential pairs S1, S2 to SN utputs differential signals D1+, D1−, D2+, D2− to DN+ and DN− to resistors RL1 and RL2 outside the current-steering DAC 10. As shown in FIG. 1, combinations of the transistors M1+ and M1−, M2+ and M2−, . . . , and MN+ and MN− are common-drain structures, so the current-steering DAC 10 is a circuit with common drains but without common sources and common gates.
As to a layout of the current-steering DAC 10, please refer to FIG. 2, which illustrates a schematic diagram of a prior art multi-transistor layout 20. The multi-transistor layout 20 includes drains 220 and 222, a source 24, and gates 260 and 262. The source 25 includes three contacts. Each of the drains 220 and 222 includes two contacts, and each of the gates 260 and 262 includes one contact. In order to conform to an electrostatic discharge (ESD) rule, manufactories set a minimum width of the drains. For example, if the minimum acceptable width of each of the drains 220 and 222 is 4 μm and areas of the contacts on the drains 220 and 222 are considered, a minimum area of each drain in the multi-transistor layout 20 is 22.7 μm2 (=4.45 μm×5.1 μm).
Please refer to FIG. 3, which illustrates a schematic diagram of a prior art multi-transistor layout 30. The multi-transistor layout 30 includes drains 320, 322, sources 340, 342, 344, and gates 360, 362, 364, 366. The drains 320, 322, the sources 340, 342, 344, and the gates 360, 362, 364, 366 can include a plurality of contacts. In FIG. 3, each of the drains 320 and 322 includes two contacts, each of the sources 340, 342, and 344 includes three contacts, and each of the gates 360, 362, 364, and 366 includes one contact. In the multi-transistor layout 20 in FIG. 2, a minimum acceptable width of each of the drains 320 and 322 is 4 μm, so a minimum area of each of the drains in the multi-transistor layout 30 is 11.73 μm2 (=4.6 μm×5.1 μm×0.5, where “0.5” means that two transistors share a drain). In comparison, for the same ESD rule, the area of each drain in the multi-transistor layout 30 is 51.7% of that of the multi-transistor layout 20.
As manufacturing processes of semiconductors progress, ESD protection becomes more and more important. For those transistors with drains connecting to pins of a chip, layouts of the drains must conform to a specific rule. Therefore, in an output end of a current-steering DAC, a drain of a transistor switch occupies a large area, induces parasitic capacitance, increases reaction time of the current-steering DAC, and decreases efficiency. In order to reduce areas of drains in a transistor having wide gates, the prior art applies layouts with finger-like, waffle-like, and n-sided polygonal shapes to layout the transistors. Please refer to FIGS. 4, 5, and 6, which illustrate schematic diagrams of finger-like, waffle-like, and n-sided polygonal layouts. In FIGS. 4, 5, and 6, notations G, D, and S represent layouts of gates, drains, and sources. As shown in FIGS. 4, 5, and 6, the finger-like, the waffle-like, and the n-sided polygonal layouts can reduce areas of the drains, but they cannot be applied for circuits with common drains but without common sources, such as the current-steering DAC 10.